The present invention relates to the field of semiconductor device design and fabrication; more specifically, it relates to a structure for structural reinforcement and support of interlevel dielectric layers and the method of fabricating said structure.
The interconnect structure of semiconductor devices comprise layers (wiring levels) containing conductive wires separated by interlevel dielectric layers (levels.) The conductive wires are electrically isolated from one another by the dielectric layers. The conductive wires in each wiring level are interconnected by conductive vias extending from the conductive wires in one wiring level, through the interlevel dielectric layer, to the conductive wires in a second wiring level. In modern semiconductor devices, the conductive wires are partially embedded in or damascened into the dielectric layers.
As the speed of modern semiconductor devices has increased, interlevel-wiring capacitance has become a problem. Methods were sought to reduce interlevel wiring capacitance. One solution that is becoming popular is the use of low-k dielectric materials such as SILK(trademark) (a polyarylene ether manufactured by Dow Chemical, Midland, Mich.), spin on glass, polyimide or other polymers. These have replaced traditional dielectric materials such a silicon oxide and silicon nitride.
A problem with low-k dielectric materials is they are not rigid like the traditional dielectric materials. Low-k materials are soft, compressible and flexible, have a low modulus and poor interfacial strength, i.e., they tend to delaminate or collapse under mechanical and thermal stress resulting in low yield, poor reliability and higher costs. Some low-k materials are brittle and tend to crack under mechanical or thermal stress. There use in semiconductor devices present two problems. First, because the conductive wires are comprised of metals (such as copper and tungsten) there is a mismatch in thermal expansion between low-k dielectrics and the metal which can lead to delamination, cracking or collapse of the low-k material during manufacture or in use in the field. Second, since the wires are formed by damascene process, which process includes a chemical-mechanical-polish (CMP) step, mechanical stress is induced into the device during CMP, which can lead to delamination, cracking or collapse.
Since low-k dielectric materials, damascene wiring levels, and CMP are basic to the fabrication of high performance semiconductor devices, a method for reducing or eliminating stress induced delamination, cracking or collapse of low-k dielectric layers is highly desirable.
A first aspect of the present invention is a semiconductor device comprising: a first wiring level having a first conductive fill shape embedded in a first dielectric; a second wiring level having a second conductive fill shape embedded in a second dielectric; and a conductive via extending between and joining the first and second conductive fill shapes.
A second aspect of the present invention is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in-each adjacent wiring level.
A third aspect of the present invention is a semiconductor device comprising: a first wiring level, the first wiring level comprising a conductive wires and a multiplicity of conductive fill shapes embedded in a first dielectric material; a multiplicity of higher wiring levels, each higher wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a second dielectric material; at least some of the fill shapes in one or more pairs of adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each pair of adjacent wiring levels.
A fourth aspect of the present invention is a semiconductor device comprising: a first wiring level having a first conductive fill shape having corners, embedded in a first dielectric; a second wiring level having a second conductive fill shape having corners, embedded in a second dielectric, the second conductive fill shape co-aligned with the first fill shape; and a conductive via aligned with each corner of the first and second fill shapes and extending between and joining the first and second conductive fill shapes.
A fifth aspect of the present invention is a semiconductor device comprising: a first wiring level having a first conductive fill shape having corners, embedded in a first dielectric; a second wiring level having a second conductive fill shape having corners, embedded in a second dielectric, the second conductive fill shape co-aligned with the first fill shape; and at least two conductive vias each aligned with a corner of the first and second fill shapes and extending between and joining the first and second conductive fill shapes.
A sixth aspect of the present invention is a method of fabricating a semiconductor device, comprising: providing a substrate; forming on the substrate, a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, forming one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level.
A seventh aspect of the present invention is a method of fabricating a semiconductor device, comprising: providing a substrate; forming a first wiring level on the substrate, the first wiring level comprising a conductive wires and a multiplicity of conductive fill shapes embedded in a first dielectric material; forming a multiplicity of higher wiring levels on the first wiring level, each higher wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a second dielectric material; at least some of the fill shapes in one or more pairs of adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, forming one or more conductive vias extending between and joining each co-aligned fill shape in each pair of adjacent wiring levels.
An eighth aspect of the present invention is a method of designing a semiconductor device having wiring levels containing wires and fill shapes interspersed with interconnecting via levels containing vias, comprising: selecting a pair of adjacent wiring levels; finding pairs of vertically aligned fill shapes in the adjacent wiring levels; and creating and placing, in the interconnecting via levels between the adjacent wiring levels, one or more vias to interconnect the pairs of fill shapes.
A ninth aspect of the present invention is A method of designing a semiconductor device having wiring levels interspersed with interconnecting via levels, comprising: placing fill shapes at least some of the wiring levels; selecting a pair of adjacent wiring levels; finding pairs of vertically aligned fill shapes in the adjacent wiring levels; and creating and placing, in the interconnecting via levels between the adjacent wiring levels, one or more vias to interconnect the pairs of fill shapes.